1. Field of the Invention
The invention relates to an integrated memory having a data line pair, which is connected to a bit line pair via at least one differential amplifier, data being transferred in the form of differential signals from the data line pair via the differential amplifier to the bit line pair and from there into memory cells connected thereto.
A memory of that type in the form of a DRAM is described by Betty Prince in "Semiconductor Memories--a Handbook of Design, Manufacture and Application," 2nd Ed., John Wiley and Sons, West Sussex, 1996, p. 258 (see FIG. 6.26a). The differential amplifier is a read/write amplifier, that is to say data can be transferred in both directions between the data line pair and the bit line pair. Only a write operation of the DRAM shall be considered in the following text. If a logic "1" is intended to be written to one of the memory cells, one line of the data line pair is brought to a high potential and the other line to a low potential. If a logic "0" is intended to be written, the potential on the two lines are interchanged relative to this.
It is customary for the two lines of the data line pair to be recharged to the same potential prior to the reading of a memory cell in a read operation (so-called precharging). By way of example, both lines of the data line pair may be brought to a high potential for this purpose. In the course of the subsequent reading of a memory cell, the content thereof influences the precharged potential on the data line pair via the bit lines and the read/write amplifier.
2. Summary of the Invention
It is accordingly an object of the invention to provide a integrated memory device, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which allows enables controlling its functions over greater distances without requiring special control lines.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
a data line pair, a bit line pair, and at least one differential amplifier connected between the data line pair and the bit line pair; PA1 memory cells connected to the bit line pair for receiving data in differential signal form from the data line pair via the differential amplifier and via the bit line pair; PA1 a control unit connected to the data line pair, the control unit: PA1 a detector unit having two inputs connected to the data line pair, the detector unit initiating a specific control function on occurrence of the second potential state on the data line pair.
setting first potential states on the data line pair corresponding to the differential signals of data to be written to the memory cells; and PA2 setting at least one second potential state on the data line pair not corresponding to any datum to be written to the memory cells;
In other words, the novel integrated memory has a control unit which, on the one hand, serves for setting first potential states on the data line pair which correspond to the differential signals of data to be written to the memory cell and, on the other hand, serves for setting at least one second potential state on the data line pair which does not correspond to any datum to be written to the memory cells.
Furthermore, the memory has a detector unit having two inputs, each of which is connected to a line of the data line pair. The detector unit initiates the desired control function when the second potential state of the data line pair occurs.
While the first potential states therefore concern those which occur on the data line pair if data corresponding to these first potential states are transferred in the form of a resultant differential signal on the data line pair via the differential amplifier to one of the memory cells (for example, first line of the data line pair low potential, second line high potential during the writing of a logic "0", high potential on the first line and low potential on the second line during the writing of a logic "1"), the second potential state does not normally occur during a write operation. One example of the second potential state is the presence of a low potential on both lines of the data line pair. The detector unit identifies the presence of this second potential state and thereupon triggers the desired control function.
The invention affords the advantage that the data line pair which is necessary in any case for writing and reading, also serves, in addition to its usual function, for communicating the second potential state to the detector unit and thus for triggering the control function. It is not necessary, therefore, to provide an additional control line in the integrated memory for this purpose, which control line would require a considerable amount of space particularly in the case of relatively large distances to be bridged. In the case of the invention, the lines of the data line pair bridge the desired distance from the control unit to the detector unit that initiates the control function.
In accordance with an added feature of the invention, the detector unit deactivates the differential amplifier on occurrence of the second potential state, i.e., when the second potential state occurs on the data line pair. If the differential amplifier is a read/write amplifier, data read from a memory cell onto the associated bit lines are thereby prevented from passing unintentionally via the differential amplifier to the data lines. This is advantageous particularly when the data line pair is connected to a plurality of differential amplifiers, each of which is connected to corresponding memory cells via a respective bit line pair. All the differential amplifiers can then be deactivated simultaneously, given the presence of the second potential state on the data line pair, by means of a respective detector unit per differential amplifier, thereby avoiding the situation where a plurality of the differential amplifiers simultaneously output data unintentionally onto the data line pair and a short circuit can thus arise. In this case, the detector units can, in a favorable manner, be arranged in a decentralized fashion directly where the desired control function is to be executed. Directly at the respective differential amplifier, therefore, in the case outlined.
In accordance with an additional feature of the invention, two activation transistors are connected between a respective input of the differential amplifier and the first and second lines of the data line pair. The activation transistors have control terminals connected to the output of the detector unit so as to receive the output signal of the detector unit.
In accordance with another feature of the invention, two data lines of the data line pair are connected to a respective input of the differential amplifier via two respective activation transistors, and one transistor of each transistor pairs has a control input connected to each data line.
In accordance with a concomitant feature of the invention:
the differential amplifier has a first operating mode in which data is forwarded from the data line pair to the bit line pair in a non-inverted state, and a second operating mode in which the data is forwarded in an inverted state; the detector unit switches the operating mode of the differential amplifier upon occurrence of the second potential state on the data line pair.
This embodiment is particularly suitable for application during a test mode of the integrated memory. This is because one and the same datum present on the data line pair can be written to the corresponding memory cell optionally in an inverted or non-inverted manner.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.